Implementation and Evaluation of Update-Based Cache Protocols Under Relaxed Memory Consistency Models
| Document type: | Journal Articles |
|---|---|
| Article type: | Original article |
| Peer reviewed: | Yes |
| Full text: | |
| Author(s): | Håkan Grahn, Per Stenström, Michel Dubois |
| Title: | Implementation and Evaluation of Update-Based Cache Protocols Under Relaxed Memory Consistency Models |
| Journal: | Future Generations Computer Systems |
| Year: | 1995 |
| Volume: | 11 |
| Issue: | 3 |
| Pagination: | 247-271 |
| ISSN: | 0167-739X |
| Publisher: | North-Holland |
| City: | Amsterdam |
| Organization: | Blekinge Institute of Technology |
| Department: | Dept. of Computer Science and Business Administration (Institutionen för datavetenskap och ekonomi) Dept. of Computer Science and Business Administration S-372 25 Ronneby +46 455 780 00 http://www.ide.hk-r.se/ |
| Authors e-mail: | hakan.grahn@ide.hk-r.se |
| Language: | English |
| Abstract: | The protocols of invalidation-based cache coherence have been extensively studied in the context of large-scale shared-memory multiprocessors. Under a relaxed memory consistency model, most of the write latency can be hidden whereas cache misses still incur a severe performance problem. By contrast, update-based protocols have a potential to reduce both write and read penalties under relaxed memory consistency models because coherence misses can be completely eliminated. This paper compares update- and invalidation-based protocols for their ability to reduce or hide memory access latencies and for their ease of implementation under relaxed memory consistency models. |
| Subject: | Computer Science\Computersystems |
| Keywords: | Multiprocessing systems, Buffer storage, Storage allocation (computer), Network protocols, Computer simulation, Synchronization, Computer hardware, Large scale systems, Performance |
