Relative Performance of Hardware and Software-Only Directory Protocols Under Latency Tolerating and Reducing Techniques

Document type: Conference Papers
Peer reviewed: Yes
Full text:
Author(s): Håkan Grahn, Per Stenström
Title: Relative Performance of Hardware and Software-Only Directory Protocols Under Latency Tolerating and Reducing Techniques
Conference name: 11th International Parallel Processing Symposium, IPPS 97 Apr 1-5 1997
Year: 1997
Pagination: 500-506
ISBN: 0818677937
Publisher: IEEE
City: Geneva, Switzerland
ISI number: A1997BH56G00073
Organization: Blekinge Institute of Technology
Department: Dept. of Computer Science and Business Administration (Institutionen för datavetenskap och ekonomi)
*** Error ***
+46 455 780 00
*** Error ***
Authors e-mail: hakan.grahn@ide.hk-r.se
Language: English
Abstract: In both hardware-only and software-only directory protocols the performance is often limited by memory access stall times. To increase the performance, several latency tolerating and reducing techniques have been proposed and shown effective for hardware-only directory protocols. For
software-only directory protocols, the efficiency of a technique depends not only on how effective it is as seen by the local processor, but also on how it impacts the software handler execution overhead in the node where a memory block is allocated. Based on architectural simulations and case studies of three techniques, we find that prefetching can degrade the performance of software-only directory protocols due to useless prefetches. A relaxed memory consistency model hides all write latency for software-only directory protocols, but the software handler overhead is virtually unaffected and now constitutes a larger portion of the execution time. Overall, latency tolerating techniques for software-only directory protocols must be chosen with more care than for hardware-only directory protocols.
Subject: Computer Science\Computersystems
Keywords: Network protocols; Data reduction; Storage allocation (computer); Program processors; Computer hardware; Computer simulation; Computer networks; Optimization; Data acquisition
Note: Also presented at 6th Workshop on Scalable Shared-Memory Multiprocessors, October 1996
Edit